The prior art teaches the formation of integrated circuits which utilize one or more FinFET type field effect transistors. The FinFET transistor comprises a channel region which is oriented to conduct an electrical current parallel to the surface of the substrate. The channel region is provided in an elongated section of semiconductor material referred to as a fin. The source and drain regions of the transistor are typically also formed in the elongated section on either side of the channel region. A gate is placed over and on both opposed sides of the elongated section at the location of the channel region to provide control over the conductive state of the transistor. This FinFET design is well suited for manufacturing a multi-channel transistor in which multiple elongated sections are formed in parallel to define neighboring channel regions that are separated from each other by an intermediate gate portion of the transistor gate spanning with a perpendicular orientation over the multiple elongated sections.
A FinFET transistor is created from at least one thin portion (referred to as the “fin”) of semiconductor material defining the elongated section used to form the channel of the transistor and also its source and drain zones. This fin is typically defined by a mask that is formed on top of a monocrystalline silicon substrate at the position of the fin. The substrate material is then directionally etched where there is no mask, to a determined depth, such that the elongated section defining the fin remains under the mask and is composed of the substrate material.
In one prior art implementation, the fin of semiconductor material which is thus obtained, and which comprises the channel of the final transistor, is not electrically insulated from the active portion of the circuit substrate, which itself is also of crystalline semiconductor material. Such a FinFET device suffers from three distinct types of leakage current. A first type of leakage current can circulate between the source and drain of the FinFET transistor, via the active portion of the substrate situated below the channel. This first leakage current, internal to each transistor, is not controlled by the potential applied to the transistor gate. A second type of leakage current arises because the channel of the FinFET transistor is also in electrical contact with the channels of other transistors of the same conductivity type via the substrate. The second leakage current flows between transistors in the form of an inter-transistor leakage current. A third type of leakage current appears between the channel of each FinFET transistor and a lower part of the substrate in response to the substrate being connected to a reference potential.
To address the leakage current issues noted above, procedures for dielectrically isolating the fin are known in the art.
In one technique, referred to as bottom oxidation through STIs (BOTS), shallow trench isolation (STI) structures are formed on either side of the fin. The silicon material of the fin is protected on a top side by barrier layer (for example, of silicon nitride) and the upper lateral sides of the fin are isolated from the STI structures by another barrier layer (also, for example, of silicon nitride). The integrated circuit wafer is then subjected to an oxidation process. The barrier layers function as oxygen (O2) barriers and only a lower (unprotected) portion of the fin (below the lateral barrier layers) is converted to a thermal oxide material which isolates the upper portion of the fin from the underlying substrate material. This process produces an undesirable scalloped interface shape at the bottom of the fin (due to the nature of the thermal oxide growth). Additionally, the process is not compatible with fins made of silicon-germanium (SiGe), and thus cannot be advantageously used when forming p-channel SiGe FinFET devices.
In another technique, referred to silicon on nothing (SON), a bottom portion of the fin is formed of silicon-germanium while an upper portion of the fin is formed of silicon. A selective etch is performed to remove the bottom SiGe portion to open a region between the underside of the Si fin and the underlying substrate. A dielectric material fill operation is then performed to fill the opened region with an insulating material. This process presents mechanical stability issues with respect to the Si fin. Additionally, complete fill of the opened region with the insulating material cannot be assured, and any voids will accordingly present tunnel fill conformality issues.
To avoid leakage currents, it is known in the art to fabricate the FinFET transistor on an integrated circuit substrate which is of the Silicon-on-Insulator (SOI) type (as opposed to the use of bulk semiconductor substrates). An SOI substrate is formed of a top semiconductor (for example, silicon or silicon-germanium) layer over an insulating (for example, silicon dioxide) layer over a bottom semiconductor (for example, silicon) substrate layer. Reference is made to U.S. Pat. No. 6,645,797, the disclosure of which is incorporated by reference, which teaches a process for realizing a FinFET transistor from an SOI substrate. The transistor which is obtained is electrically insulated from the lower part of the substrate by the intermediate layer of insulating material, and thus leakage current concerns are reduced.
Further substrate development has reduced the thickness of the intervening insulating layer to about 50 nm to produce a substrate for use in transistor fabrication that is referred to as an extremely thin silicon on insulator (ETSOI) substrate. Still further substrate development has reduced the thicknesses of all substrate layers to produce a substrate for use in transistor fabrication that is referred to an ultra-thin body and buried oxide (UTBB) substrate where the thickness of the intervening insulating layer is about 25 nm (or less) and the thickness of the top semiconductor layer is about 5 nm to 10 nm. All of these substrates may more generally be referred to as SOI substrates.
The FinFET transistor implemented on an SOI substrate is considered by those skilled in the art as an attractive option for use in connection with circuits fabricated at aggressively scaled process technology nodes, and in particular is well suited for use in CMOS integrated circuit designs. Superior short channel control along with higher performance in comparison to conventional planar bulk devices are recognized as advantages associated with the selection of the FinFET for CMOS circuits.
Notwithstanding the foregoing, it is difficult with the SOI implementation to introduce stress to the channel region. There is a need in the art to provide both some form of fin isolation and further add stress to the channel.